In this assignment, you will design a differential amplifier as shown in the sch

In this assignment, you will design a differential amplifier as shown in the schematics below.

Your design should satisfy the required differential gain, input impedance, single-ended common-mode
gain, and the power dissipation specifications provided in Section A below. Then in Sections B and C, you
will simulate your circuit on LTSpice to compare the simulation results with hand calculations.

A. Hand design: Design the bipolar differential amplifier and the current source and bias network
(𝑅1, 𝑄3, π‘Žπ‘›π‘‘ 𝑄4) above such that:

(i) Differential gain: 𝐴𝑑 β‰₯ 200 𝑉,
𝑉

(ii) Input differential resistance: 𝑅𝑖𝑑 β‰₯ 50 π‘˜Ξ©,
(iii) π΄π‘π‘š < 0.1 where π΄π‘π‘š is the single-ended common-mode gain, defined as the gain for a common-
mode input signal when the output is measured from one of the outputs with respect to ground, rather
than differentially.
(iv) To maximize battery life, the power consumption of the differential amplifier, 𝑃𝑇𝑂𝑇𝐴𝐿, must be less
than 2 milliwatts.

Design Suggestion for Part A.
1. Derive the expression for 𝑅 , ignoring π‘Ÿ of Q1 and Q2.). Replace small signal parameters with

𝑖𝑑 π‘œ

β€œDC currents”, β€œresistors”, β€œπ‘‰ β€œ, β€œπ›½β€, β€œπ‘‰ β€œ, etc., use specific values (e.g., 𝑉 = 100 𝑉, 𝛽 = 200,
𝑑h𝐴 𝐴

etc.), and simplify the expressions. The 𝑅𝑖𝑑 design specification will help determine an upper limit
for the DC collector current of Q1 (and Q2 since 𝐼𝐢1 = 𝐼𝐢2).

2. The total power dissipation is 𝑃
𝑇𝑂𝑇𝐴𝐿

=𝑃 +𝑃 =9𝑉×(𝐼 +𝐼 ). Here, 𝐼 is the
𝑉𝐷𝐷 𝑉𝑆𝑆 𝑉𝐷𝐷 𝑉𝑆𝑆 𝑉𝐷𝐷

sum of all DC currents leaving the +𝑉
𝐷𝐷

and 𝐼 is the sum of all dc currents entering the βˆ’π‘‰ .
𝑉𝑆𝑆 𝑆𝑆

Express 𝐼𝑉𝐷𝐷 and 𝐼𝑉𝑆𝑆 in terms of the collector currents of Q1 (or Q2), ignoring the current in the

reference current generation branch formed by 𝑅1 and 𝑄4. The 𝑃𝑇𝑂𝑇𝐴𝐿 design specification will
help determine another upper limit for 𝐼𝐢1 = 𝐼𝐢2.

  1. Derive expressions for 𝐴 and 𝐴 . When deriving 𝐴 , include π‘Ÿ of Q1 or Q2. When deriving 𝐴
    π‘‘π‘π‘šπ‘‘π‘œ π‘π‘š
    ignore π‘Ÿ of Q1 and Q2 but include π‘Ÿ of Q3. Replace small signal parameters with β€œDC currents”,
    π‘œπ‘œ
    β€œresistors”, β€œπ‘‰ β€œ, β€œπ›½β€, β€œπ‘‰ β€œ, etc., use specific values (e.g., 𝑉 = 100 𝑉, 𝛽 = 200, etc.), and
    𝑑h𝐴 𝐴
    simplify the expressions. The 𝐴𝑑 and π΄π‘π‘š design specifications will respectively provide lower and
    upper limits for the product 𝑅𝐢 Γ— 𝐼𝐢1.
  2. Consider the forward-active region requirement of Q1 (or Q2). For 𝑉 = 0 𝑉, find another upper
    𝐢𝑀
    limit for the product 𝑅𝐢 Γ— 𝐼𝐢1.
  3. Pick an 𝐼𝐢1 satisfying all upper limits for 𝐼𝐢1 found in steps 1 and 2. Find 𝑅1 based on the value you
    pick for 𝐼𝐢1. Pick an 𝑅𝐢 satisfying the upper and lower limits for 𝑅𝐢 βˆ— 𝐼𝐢1 found in steps 3 and 4.

Inyoursimulations,usetheBJTmodel2N2222ofNXP,whichhasaSPICEmodelasbelowwith𝑉 and𝛽

highlighted:

𝐴

B. DC Analysis: In LTSpice do a DC operating point simulation (.op) with both inputs connected to ground
(i.e.,𝑉 =0𝑉).DeterminethesimulatedDCvaluesfor𝐼 ,𝐼 ,𝐼 ,𝐼 ,𝐼 ,𝑉 ,𝑉 ,𝑉 ,𝑉 .Compare

𝐢𝑀 𝑅1𝐢3𝐢4𝐢1𝐢2 𝐡3 𝐸1,2 𝑂1 𝑂2
these results with your hand calculations. Additionally, comment on the matching between 𝐼𝑅1 π‘Žπ‘›π‘‘ 𝐼𝐢3
and comment on the calculated vs. simulated match between 𝐼𝑅1 π‘Žπ‘›π‘‘ 𝐼𝐢3.

C. Transient Analysis: In LTSpice do a transient simulation (.tran) for 100 ms.
For differential small-signal input simulations:

Apply 𝑣 =1π‘šπ‘‰ π‘ π‘–π‘›π‘’π‘ π‘œπ‘–π‘‘π‘Žπ‘™π‘ π‘–π‘”π‘›π‘Žπ‘™π‘Žπ‘‘100𝐻𝑧. [i.e., 𝑣 =+𝑣𝑖𝑑 =0.5π‘šπ‘‰sin(2βˆ—πœ‹βˆ—100π»π‘§βˆ—π‘‘)

𝑖𝑑 𝑝 𝑖𝑑1

2

and𝑣𝑖𝑑2 =βˆ’π‘£π‘–π‘‘ =0.5π‘šπ‘‰sin((2βˆ—πœ‹βˆ—100π»π‘§βˆ—π‘‘)+πœ‹)withDCoffset=0V.]
2

𝑣 =𝑣 =𝑣
π‘–π‘π‘š1 π‘–π‘π‘š2 π‘π‘š

For common-mode small-signal input simulations:
Apply 𝑣 =1π‘šπ‘‰ π‘ π‘–π‘›π‘’π‘ π‘œπ‘–π‘‘π‘Žπ‘™π‘ π‘–π‘”π‘›π‘Žπ‘™π‘Žπ‘‘100𝐻𝑧. [i.e.,

=1π‘šπ‘‰sin(2βˆ—πœ‹βˆ—

π‘π‘š 𝑝
100𝐻𝑧 βˆ— 𝑑) with DC offset = 0V.]

1. For the differential small-signal input, what is the expected emitter voltage of Q1 and Q2,
𝑣𝑒1(= 𝑣𝑒2)? Plot the simulated waveform. What is the simulated value of 𝑣𝑒1(= 𝑣𝑒2)?

2. Plot 𝑣𝑖𝑑, π‘£π‘œπ‘‘(π‘£π‘œπ‘‘ = π‘£π‘œ2 βˆ’ π‘£π‘œ1), π‘Žπ‘›π‘‘ 𝑖𝑖𝑑. Note that 𝑖𝑖𝑑 is the base current of Q1 (𝑖𝑖𝑑 = 𝑖𝑏1).
Calculate the simulated 𝐴𝑑 = π‘£π‘œπ‘‘ /𝑣𝑖𝑑 and 𝑅𝑖𝑑 = 𝑣𝑖𝑑 /𝑖𝑖𝑑 . Compare the values with your
design targets.

3. If the simulation results do not match the design constraints, revisit your design to achieve
the targets.

4. For the common-mode small-signal input, plot π‘£π‘π‘š and π‘£π‘œπ‘π‘š . (π‘£π‘œπ‘π‘š = π‘£π‘œπ‘π‘š2 =
π‘£π‘œπ‘π‘š1 𝑀h𝑒𝑛 𝑑h𝑒 𝑖𝑛𝑝𝑒𝑑 𝑖𝑠 π‘Ž π‘π‘œπ‘šπ‘šπ‘œπ‘› βˆ’ π‘šπ‘œπ‘‘π‘’ π‘ π‘–π‘”π‘›π‘Žπ‘™)

Report Requirements
A. Your hand calculations for part A must be detailed and sequential. Show every step of the derivations
clearly, and explain how and why you select each parameter, including any approximations made.
B and C. For parts B and C, besides answering the questions and plotting the requested simulation results,
complete the table below. Provide explanations for any discrepancies exceeding 10%.

𝐼𝑅1 𝐼𝐢4 𝐼𝐢3

𝐼𝐢1 𝐼𝐢2

Hand
calculations
Simulated

Percent
discrepancy

Hand
calculations
Simulated

Percent
discrepancy

𝑉𝑉𝑉𝑉𝐴𝑅𝐴
𝐡3 𝐸1,2 𝑂1 𝑂2 𝑑 𝑖𝑛 π‘π‘š